// 打一拍操作
`include "defines.v"
module id_ex(
           input wire clk,
           input wire rst,

           // from id
           input wire [31: 0] inst_i,
           input wire [31: 0] inst_addr_i,
           input wire [31: 0] opl_i,
           input wire [31: 0] op2_i,
           input wire [4: 0] rd_addr_i,
           input wire reg_wen_i,

           //to ex
           output wire [31: 0] inst_o,
           output wire [31: 0] inst_addr_o,
           output wire [31: 0] op1_o,
           output wire [31: 0] op2_o,
           output wire [4: 0] rd_addr_o,
           output wire reg_wen_o
       );

dff_set#(
           .DW ( 32 )
       )u_dff_set_id_ex1(
           .clk ( clk ),
           .rst ( rst ),
           .set_data ( `INST_NOP ),
           .data_i ( inst_i ),
           .data_o ( inst_o )
       );

dff_set#(
           .DW ( 32 )
       )u_dff_set_id_ex2(
           .clk ( clk ),
           .rst ( rst ),
           .set_data ( 32'b0 ),
           .data_i ( inst_addr_i ),
           .data_o ( inst_addr_o )
       );

dff_set#(
           .DW ( 32 )
       )u_dff_set_id_ex3(
           .clk ( clk ),
           .rst ( rst ),
           .set_data ( 32'b0 ),
           .data_i ( opl_i ),
           .data_o ( op1_o )
       );


dff_set#(
           .DW ( 32 )
       )u_dff_set_id_ex4(
           .clk ( clk ),
           .rst ( rst ),
           .set_data ( 32'b0 ),
           .data_i ( op2_i ),
           .data_o ( op2_o )
       );

dff_set#(
           .DW ( 5 )
       )u_dff_set_id_ex5(
           .clk ( clk ),
           .rst ( rst ),
           .set_data ( 5'b0 ),
           .data_i ( rd_addr_i ),
           .data_o ( rd_addr_o )
       );

dff_set#(
           .DW ( 1 )
       )u_dff_set_id_ex6(
           .clk ( clk ),
           .rst ( rst ),
           .set_data ( 1'b0 ),
           .data_i ( reg_wen ),
           .data_o ( reg_wen_o )
       );

endmodule
